A negative-capacitance (NC) in nanoscale devices have been previously developed to provide voltage amplification for low power nanoscale devices such as FinFETs and metal-oxide-semiconductor field-effect transistors (MOSFETs). NC MOSFETs (NC-FETs) have been recently developed which utilizes a ferroelectric (FE) material to achieve negative capacitance and modulate gate voltage to achieve low subthreshold swing (SS) of MOSFET. In order to achieve low power consumption for Internet of Things (IoT) applications, a low voltage drain bias (Vdd) is needed which requires a low SS of the MOSFET. Current devices do not meet these criteria.
Current devices include a negative capacitor fabricated on top of a complementary-metal-oxide semiconductor (CMOS), wherein the negative capacitor is operated as a voltage gain (Vg) amplifier. Challenges of incorporating FE into gate-first or gate-last processes exist. With gate-first processing, the FE material suffers from a high thermal budget of a source/drain (S/D) annealing, resulting in generation of defects, high leakage and voltage (Vt) hysteresis. When FE material is incorporated in gate-last CMOS processing, it is difficult to fill two gate stacks in a short gate length trench. Moreover, existing gate-last n-type metal gates cannot withstand annealing temperature (e.g., 600° C.), which limits the FE material engineering.
It is critical to match the capacitance between the FE and CMOS. As a result, a NC-FET process with tunable NC is critical for a NC-FET application. With conventional structures challenges exist with having non-hysteretic NC-FET for various width/length (W/L) scaling. As gate length (L) changes, the FE/gate oxide and Si substrate cap scale, however, the gate-to-drain cap does not. When a “balance” is lost NC-FET no longer operates like a proper NC-FET. As device width (W) changes, the balance changes as well. For extended gate (EG) and double gate (DG) FETs with a thick oxide input/output (I/O), which have a much different gate cap compared to single gate (SG) FETs, there is no clear way to “balance” and obtain a negative cap on both types of FETs. Accordingly, there exist concerns about the ease of design, namely how to obtain the behavior across all L and W dimensions for both SG and EG/DG devices.
A need therefore exists for methodology enabling the formation of NC-FET with existing CMOS processing and the resulting device.